1. Field of the Invention
This invention relates to a buffer circuit for wide use which is formed on an insulating substrate using a thin film transistor of a single channel and can be used in various applications, devices and products. More specifically, the present invention relates to a semiconductor device, a display panel and an electronic apparatus.
2. Description of the Related Art
In a low temperature poly-silicon (LTPS) process, a circuit can be formed using both of an N-channel metal oxide semiconductor (NMOS) type thin film transistor (TFT) and a P-channel-metal oxide semiconductor-(PMOS) type thin film transistor. Accordingly, in the low temperature poly-silicon process, the two types of thin film transistors are usually used to fabricate a circuit called complementary metal oxide semiconductor (CMOS) circuit.
On the other hand, in the case of CMOS circuit since the two types of thin film transistors must be used, an increased number of fabrication steps are demanded in the end. The increase of the number of steps makes a cause of lowering the fabrication efficiency and raising the fabrication cost.
Accordingly, even where a poly-silicon process is used, if possible, it is desirable to implement a circuit having a same function as that of a CMOS circuit by using only a thin film transistor of a single channel, that is, only a thin film transistor of the NMOS type or of the PMOS type.
Besides, a single channel circuit of the type described can be applied also where a circuit is formed from amorphous silicon or organic semiconductor.
For example, in the case of amorphous silicon, a circuit can be fabricated only with a thin film transistor of the NMOS type, but in the case of an organic TFT, a circuit can be fabricated only with a thin film transistor of the PMOS type.
From such background, it is demanded to implement a circuit wherein operation of a function same as that of a CMOS circuit can be executed by using only a thin film transistor of a single channel, that is, only a thin film transistor of the NMOS type or of the PMOS type.
In the present specification, attention is paid particularly to a buffer circuit. The buffer circuit is a general purpose circuit which is incorporated in various circuits. Accordingly, basically the application of the buffer circuit is not limited to a specific application. However, in the following description, the buffer circuit is applied to a driving circuit for driving a display panel for the convenience of description.
In the following, an example of an existing buffer circuit applied to a driving circuit for an organic EL panel of the active matrix driving type is disclosed.
FIG. 1 shows an example of a system configuration of an organic EL panel. Referring to FIG. 1, the organic Electro Luminescence (EL) panel 1 shown includes a pixel array section 3, a signal line driving section 5, a first control line driving section 7 and a second control line driving section 9 disposed on a panel board.
A plurality of sub pixels 11 are disposed in a matrix in accordance with a display resolution in the pixel array section 3. Examples of an equivalent circuit of a sub pixel 11 are shown in FIGS. 2 and 3. It is to be noted that all of the sub pixels 11 shown in FIGS. 2 and 3 are formed only from NMOS thin film transistors.
Referring to FIGS. 2 and 3, a sampling transistor is denoted by N1, a driving transistor by N2, a lighting control transistor by N3, and a storage capacitor by Cs. Referring also to FIG. 1, a writing control line is denoted by WSL, a lighting control line by LSL, and a current supply line by PSL.
Incidentally, FIG. 2 shows an equivalent circuit having a circuit configuration where a driving method wherein a turning on operation and a turning off operation of an organic EL element organic light emitting diode (OLED) are implemented by on/off control of the lighting control transistor N3 is adopted.
Meanwhile, FIG. 3 shows an equivalent circuit having a circuit configuration where another driving method wherein a turning on operation and a turning off operation of an organic EL element OLED are implemented by a potential variation of the lighting control line LSL. It is to be noted that, in the circuit of FIG. 3, the lighting control line LSL functions also as a current supply source.
FIGS. 4A to 4C are timing charts when a signal potential Vsig (data) is written into a sub pixel 11 shown in FIGS. 2 and 3. In particular, FIG. 4A illustrates a driving waveform of a signal line DTL. A signal potential Vsig corresponding to a pixel gradation Data is supplied to the signal line DTL. The magnitude of driving current to be supplied from the driving transistor N2 depends upon the magnitude of the signal potential Vsig. The organic EL element OLED is a current-driven element and exhibits a luminance which increases as the driving current increases.
FIG. 4B illustrates a driving waveform of the writing control lines WSL. Within a period within which the writing control lines WSL exhibits the H level, the sampling transistor N1 is controlled to an on state, and thereupon, the potential of the signal line DTL is written into the gate electrode of the driving transistor N2.
FIG. 4C illustrates a driving waveform of the lighting control line LSL. The lighting control line LSL is driven with two values of the H level and the L level. By changeover of the potential of the lighting control line LSL, the organic EL element OLED is controlled for changeover between on and off states, that is, between a light emitting state and a no-light emitting state.
It is to be noted that the control amplitude of the lighting control line LSL is different between the sub pixel 11 shown in FIG. 2 and the sub pixel 11 shown in FIG. 3. This is because, while, in the sub pixel 11 shown in FIG. 2, it is only necessary for the lighting control line LSL to be able to drive the lighting control transistor N3, in the sub pixel 11 shown in FIG. 3, it is necessary for the lighting control line LSL to supply an operating voltage to both of the driving transistor N2 and the organic EL element OLED.
As seen from FIGS. 4A to 4C, after writing of the signal potential Vsig ends, when the lighting control line LSL has the H level, the organic EL element OLED exhibits an on state to emit light, but when the lighting control line LSL exhibits the L level, the organic EL element OLED exhibits an off state and emits no light.
It is to be noted that the peak luminance level can be controlled by variably controlling the ratio or duty of the light emitting period occupying in a one-field period.
In addition, the lighting control line LSL (FIG. 4C) is used also for adjustment of a moving picture characteristic. For the adjustment of the moving picture characteristic, it is demanded to adjust the number of times of turning on within a one-field period or the timing of a light emitting period.
Accordingly, it is demanded for the second control line driving section 9 to be able to output a plurality of kinds of pulses.
Besides, where the active matrix driving method is applied to a popular line-sequential writing method, such pulse waves as described above must be able to be transferred line-sequentially.
In particular, it is demanded for a driving section for a control line of the type described to have incorporated therein two functions including a function of freely setting the pulse length of the control pulses and another function of transferring the pulses line-sequentially to the succeeding stage.
Incidentally, in the sub pixels 11 shown in FIGS. 2 and 3, the writing operation of the signal potential Vsig described above sometimes involves a threshold value correction operation and a mobility correction operation of the driving transistor N2.
FIGS. 5A to 5F show timing charts of the sub pixel 11 shown in FIG. 2. It is to be noted that, where the sub pixel 11 of FIG. 2 has a correction function, the current supply line PSL is driven in such a manner as seen in FIG. 5C. Meanwhile, FIGS. 6A to 6E show timing charts of the sub pixel 11 of FIG. 3. It is to be noted that the sub pixel 11 shown in FIG. 2 and the sub pixel 11 shown in FIG. 3 are different from each other in whether or not an initialization operation and light emitting period control are separated from each other.
In the light emitting period control, an operation for varying the ratio between a light emitting period and a no-light emitting period, that is, the duty, is demanded in order to adjust the peak luminance. Further, in the light emitting period control, an operation of changing the number of times of changeover between a light emitting period and a no-light emitting period within a one-field period is demanded in order to adjust the moving picture display characteristic. For such applications, the circuit configuration of the second control line driving section 9 is generally complicated.
Accordingly, the circuit configuration of FIG. 2 wherein the supply line (PSL) for an initialization pulse for providing a preparation timing for a threshold value correction period and the supply line (LSL) for a lighting period control pulse are prepared separately is advantageous in simplification of the control interface. However, the circuit configuration of FIG. 2 demands three control lines including the writing control lines WSL, lighting control line LSL and current supply line PSL.
In the following description, a threshold value correction operation, a mobility correction operation and a control operation of a sub pixel 11 including a light emitting period control are described in regard to the pixel circuit shown in FIG. 3. Accordingly, the following description is given with reference to FIG. 6.
It is to be noted that the control operation used for the pixel circuit shown in FIG. 2 is common to that used for the pixel circuit shown in FIG. 3 except that the initialization operation and the light emitting period control are separated from each other as described above. Therefore, description of the control operation for the pixel circuit shown in FIG. 2 is omitted herein to avoid redundancy.
FIG. 6A shows a driving waveform of the writing control line WSL. For example, within a period within which the writing control line WSL has the H level, the sampling transistor N1 is controlled to an on state. Consequently, the potential of the signal line DTL is written into the gate electrode of the driving transistor N2.
It is to be noted that the first H level period in FIG. 6A is used for dispersion correction of the threshold potential Vth of the driving transistor N2.
On the other hand, the second H level period in FIG. 6A is used for writing of a signal potential Vsig corresponding to a pixel gradation and also for dispersion correction of the mobility μ of the driving transistor N2.
Incidentally, the reason why the waveform of the falling edge of the second H level period is inclined is that it is intended to set an optimum mobility correction period with regard to all gradations from a high luminance, that is, a high signal potential, to a low luminance, that is, a low signal potential.
The mobility correction is an operation for correcting a mobility difference between a driving transistor N2 whose mobility μ is high and another driving transistor N2 whose mobility μ is low, and the correction time for the mobility correction is defined by the length of the H level of the writing control lines WSL. In principle, as the luminance decreases, that is, as the signal potential decreases, the demanded correction time increases.
FIG. 6B shows a driving waveform of the signal line DTL. Two different potentials are applied to the signal line DTL. An offset potential Vofs is for the threshold value correction of the driving transistor N2. A signal potential Vsig provides a pixel gradation. The magnitude of the driving current to be supplied by the driving transistor N2 depends upon the magnitude of the signal potential Vsig. The organic EL element OLED is a current driven element and exhibits a higher luminance as the driving current increases.
FIG. 6C shows a driving waveform of the lighting control line LSL. The lighting control line LSL is driven with two values of the H level and the L level. The first L level period in FIG. 6C is used to define an initialization period. The second L level period in FIG. 6C is used to define a no-light emitting period (turning off period) after light emission is started.
The initialization operation here is an operation for expanding the gate-source voltage Vgs of the driving transistor N2 from the threshold voltage Vth. This operation is essentially demanded before execution of threshold value correction. The operation is hereinafter referred to as correction preparation operation.
After this correction preparation operation, the offset potential Vofs is applied to the gate electrode of the driving transistor N2 and the potential of the lighting control line LSL is changed over to the H level. Operation in this potential relationship is the threshold value correction operation. After the threshold value correction operation is started, the source potential Vs of the driving transistor N2 gradually rises, and the rise of the source potential Vs stops at a point of time at which the gate-source voltage Vgs of the driving transistor N2 reaches the threshold voltage Vth.
It is to be noted that, after the writing of the signal potential Vsig ends, a light emitting period is started and continues till a next writing period. Within the light emitting period, when the lighting control line LSL has the H level, the organic EL element OLED is controlled to an on state to emit light, but when the lighting control line LSL has the L level, the organic EL element OLED is controlled to an off state to emit no light. The peak luminance level can be controlled by variably controlling the ratio of the light emitting period length within a one-field period.
FIG. 6D illustrates the potential Vg appearing at the gate electrode of the driving transistor N2. FIG. 6E illustrates the potential Vs appearing at the source electrode of the driving transistor N2, that is, at the anode of the organic EL element OLED.
As described hereinabove, it is necessary for the pulse length of the write control signal of FIG. 6A or the lighting control signal of FIG. 6C to be different in response to an object of the driving operation.
For example, in the former case, it is necessary for the pulse length to be different between that in the threshold value correction operation and that in the signal writing and mobility correction operation. On the other hand, for example, in the latter case, it is necessary for the pulse length to be different between that within a period of the correction preparation operation and that during the turning on/off control within the light emitting period.
Accordingly, it is demanded for the first control line driving section 7 and the second control line driving section 9 to be capable of outputting a plurality of different pulse lengths. Besides, in the case of the line-sequential writing method which is popular in the active matrix driving method, such pulse waveforms must be transferred line-sequentially. In other words, a control line driving section of the type described is demanded to have two different functions incorporated therein including a function of freely setting the pulse length of control pulses and another function of capable of transferring the control pulse line-sequentially to the succeeding stage.
FIGS. 7 to 14 illustrate an example of a control line driving circuit which satisfies the driving conditions described hereinabove and examples of driving operation of the control line driving circuit. It is to be noted that the control line driving circuit is formed from a shift register.
The shift register shown in FIG. 7 is formed from a series circuit of 2N shift stages SR(1) to SR(2N). Each shift stage uses output pulses of other shift stages positioned at the directly preceding and succeeding stage positions as driving pulses such that a clock signal inputted to the self stage is extracted as an output pulse.
FIGS. 8A to 8I show driving pulse waveforms of the shift resister. It is to be noted that FIGS. 8A to 8I show pulse waveforms where the shift register is formed from only NMOS type thin film transistors.
FIG. 8A shows a start pulse st for driving the first shift stage, and FIG. 8B shows an end pulse end for driving the 2Nth shift stage. FIG. 8C shows a clock signal ck1 for shift stages at even-numbered stage positions.
FIG. 8D shows a clock signal ck2 for shift stages at odd-numbered stage positions, and FIG. 8E shows an output pulse o1 of the first shift stage SR(1). FIG. 8F shows an output pulse o(k−1) of the k−1th shift stage SR(k−1). FIGS. 8G to 8I show output pulses o at the stages represented by respective reference characters denoted therein.
FIG. 9 shows an example of an internal circuit of a shift stage SR positioned at the kth stage position. Referring to FIG. 9, all thin film transistors which form the shift stage SR are of the NMOS type. The output stage of the shift stage SR is formed from thin film transistors N11 and N12 of the NMOS type connected in series between a power supply potential VSS and the clock input terminal. It is to be noted that a node between the thin film transistors N11 and N12 is connected to the output terminal. Further, an interpolation capacitor Cb1 is connected between the gate electrode of the thin film transistor N11 and the power supply potential VSS. Meanwhile, another interpolation capacitor Cb2 is connected between the gate electrode of the thin film transistor N12 and the clock input terminal. This interpolation capacitor Cb2 interpolates a bootstrap operation.
FIGS. 10A to 10F illustrate input and output pulses of the shift stage SR and a potential relationship between the nodes A and B. In particular, FIG. 10A shows a waveform of a clock signal ck. FIG. 10B shows a waveform of a first driving pulse in1(k) which is an output pulse out(k−1) of the shift stage positioned at the preceding stage position. FIG. 10C shows a waveform of a second driving pulse in2(k) which is an output pulse out(k+1) of the shift stage positioned at the succeeding stage position. FIG. 10D shows a waveform of the potential at the node B which is a control wiring line potential of the thin film transistor N11. FIG. 10E shows a waveform of the potential at the node A which is a control wiring line potential of the thin film transistor N12. FIG. 10F shows a waveform of the output pulse out appearing at the output terminal.
As seen from FIGS. 10A to 10F, the potentials at the node A and the node B are changed over complementarily to each other at a timing at which the first driving pulse in1(k) rises to the H level and at another timing at which the second driving pulse in2(k) rises to the H level. It is thin film transistors N13 to N16 to implement the complementary operation each other.
For example, when the first driving pulse in1(k) has the H level and the second driving pulse in2(k) has the L level, the thin film transistors N13 and N14 exhibit an on state while thin film transistors N15 and N16 exhibit an off state. Further, for example, when the first driving pulse in1(k) has the L level and the second driving pulse in2(k) has the H level, the thin film transistors N15 and N16 exhibit an on state and the thin film transistors N13 and N14 exhibit an off state.
Incidentally, while the node A has the H level, the interpolation capacitor Cb2 is charged. Therefore, if, while the node A has the H level, the clock signal ck is changed over to the H level and the H level appears at the output pulse out(k), then the potential at the node A changes so as to rise by an amount corresponding to the charged voltage of the interpolation capacitor Cb2. At this time, since the gate-source voltage Vgs of the thin film transistor N12 is secured higher than the threshold voltage Vth by a bootstrap operation, the potential waveform of the output pulse out(k) is quite same as that of the clock signal ck.
In other words, the shift register shown in FIG. 7 operates so as to extract the clock signal ck from the shift stages beginning with the first shift stage and output the clock signal ck to the output terminal. Accordingly, in this shift register, the range of variation of the pulse width of the output pulse out is restricted within a 1H period, that is, within one horizontal scanning period, within which the pulse width of the clock signal ck can be varied.
It is to be noted that the shift register can transfer a plurality of pulse signals within a 1H period.
FIGS. 11A to 11I illustrate an example of a transfer operation where the clock signal ck is formed from two pulse signals. The waveforms shown in FIGS. 11A to 11I correspond to those of FIGS. 8A to 8I, respectively.
FIGS. 12A to 12F illustrate operation waveforms of the corresponding shift stage SR. The waveforms of FIGS. 12A to 12F correspond to those of FIGS. 10A to 10F, respectively. As seen in FIG. 12E, also a bootstrap operation is executed for two pulse signals.
Further, the shift register shown in FIG. 7 can reproduce the same waveform variation on the output pulse out by adjustment of the rising speed and the falling speed of the clock signal ck.
FIGS. 13A to 13I illustrate an example of a transfer operation where a clock signal ck of a trapezoidal waveform is inputted. It is to be noted that the waveforms shown in FIGS. 13A to 13I correspond to those of FIGS. 8A to 8I, respectively.
Further, FIGS. 14A to 14F show operation waveforms of the shift stage SR in this instance. The waveforms of FIGS. 14A to 14F correspond to those of FIGS. 10A to 10F, respectively. As seen from FIG. 14E, also a bootstrap operation produces a trapezoidal waveform quite same as that of the clock signal ck, and the resulting waveform is extracted as the output pulse out.
A similar shift register circuit disclosed in Japanese Patent Laid-Open No. 2005-149624.